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Package, like 6-lead dip package with 1.27mm pin pitch, compatible with SOIC-8, 3.9x4.9mm² body, exposed pad, thermal vias, http://www.ti.com/lit/ds/symlink/drv8870.pdf 20-Pin Thermally Enhanced Thin Shrink Small Outline (SS)-5.30 mm Body [DFN] (see Microchip Packaging Specification 00000049BS.pdf DFN, 10 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/00001725D.pdf (Page 12)), generated with kicad-footprint-generator ipc_gullwing_generator.py TSSOP, 40 Pin (JEDEC MO-153 Var CD https://www.jedec.org/document_search?search_api_views_fulltext=MO-153), generated with kicad-footprint-generator Molex KK 396 Interconnect System, old/engineering part number: 22-27-2031, 3 Pins per row (https://www.molex.com/pdm_docs/sd/022057045_sd.pdf), generated with kicad-footprint-generator Soldered wire connection.

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