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BackHardware/Panel/precadsr-panel-Gerbers/precadsr-panel.gbrjob Normal file View File # For PCBs designed using KiCad: https://www.kicad.org/ # Format documentation: http://kicad-pcb.org/help/file-formats/ # Temporary files *.lck # KiCad backups folders *-backups # Compressed files *.zip # Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes are merged with plated holes count 16 ============================================================= Total unplated holes count 0 Hardware/Panel/precadsr-panel-Gerbers/precadsr-panel-CmtUser.gbr Normal file Unescape Hardware/PCB/precadsr/ao_tht.pretty/Potentiometer_Alpha_RD901F-40-00D_Single_Vertical_CircularHoles.kicad_mod Normal file Unescape Schematics/SynthMages.pretty/eurorack_rail_hole.kicad_mod Normal file View File Panels/title_test_22.stl Normal file View File Merge pull request 'new_footprints' (#5) from new_footprints into main Merge pull request 'Put title box in PDF export Put title box in PDF export Merge pull request synth_mages/MK_VCO#5 Merge pull request 'Fix rail clearance issues, make all power traces large "rules": { PCB initial layout, no traces .
- 3.527984e-03 -6.087880e-02 facet normal.
- 1.021420e+01 vertex -1.071780e+02 9.665134e+01.
- SPT 2.5/5-H-5.0 1991008 Connector Phoenix Contact connector footprint.
- 137.23 (end 171.6 134.3475.