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Back"Layer B.Paste" "Notes": "Layer B.SilkS" ; DRILL file {KiCad 7.0.11-7.0.11~ubuntu22.04.1} date Tue Mar 5 20:19:51 2024 Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) T5 15.200mm 0.5984" (1 hole) T3 7.000mm 0.2756" (6 holes) T4 10.000mm 0.3937" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole Total plated holes count 16 Not plated through holes: ============================================================= From a22bca6d29ddc0a54597dab4d11ad9ab7e48e3c6 Mon Sep 17 00:00:00 2001 Subject: [PATCH 02/13] More notes Schematics/schematic_bugs_v1.txt | 2 | 10R | Resistor | | | Screws, nuts, and spacers (see build notes) 1 SIP socket, 2.54 mm, 1x2 (see [build notes](build.md | | | | | | | J2 | 1 | LM358 | Low-Power, Dual Operational Amplifiers, DIP-14/SOIC-14 | | | | R9, R11, R13 | 3 | 4.7k | Resistor | | R21, R22, R23 | 3 pin Molex header 2.54 mm spacing Pin header 2.54 mm spacing
- 1.510160e-01 2.163423e-03 9.885290e-01 vertex -1.077753e+02.
- Normal -4.866816e-001 8.343551e-001 2.588294e-001 vertex 3.447419e+000 -3.878611e+000 2.475471e+001.