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BackSocket # Temporary files *.lck # KiCad backups folders temp_* # Compressed files *.zip # Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes are merged with plated holes count 0 Minor layout tweaks Finish schematic, add PDF' (#2) from schematic by Eeschema 5.1.10-88a1d61d58~90~ubuntu20.04.1 **Component Count:** 76 Docs/precadsr_layout_back.pdf Normal file Unescape Hardware/PCB/precadsr/ao_tht.pretty/C_Disc_D3.0mm_W1.6mm_P2.50mm.kicad_mod Normal file View File 3D Printing/Cases/Eurorack Modular Case/20210926_092147.jpg Executable file View File 3D Printing/Cases/Eurorack Modular Case/DSC03768.JPG Executable file View File 3D Printing/Panels/AD&D 1e spell names in Filmoscope Quentin/Panels/BLADE BARRIER.png' Delete '3D.
- Vertex 4.25779 -9.04827 0 facet.
- Pin (https://www.diodes.com/assets/Datasheets/PAM8403.pdf), generated with kicad-footprint-generator.
- Normal -5.026217e-001 8.616821e-001 6.982454e-002 vertex 1.333511e+000 -3.920723e+000 2.470218e+001.
- 132 Pins, 0.5mm Pitch, https://www.diodes.com/assets/Datasheets/AP22913.pdf WLCSP-4, 0.64x0.64mm, 4.