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BackThe glide capacitor (C13) is connected to trigger, gate jack is normalized\nto +12 V, 10 mA -12 V ## Photos [to be added] ## Documentation: ### Documentation: * [Schematic](Docs/precadsr.pdf) * PCB layout: [front](Docs/precadsr_layout_front.pdf), [back](Docs/precadsr_layout_back.pdf ## Git repository From 40ce306867b3d353457e134a232ee65f5767bece Mon Sep 17 00:00:00 2001 Latest commits for file Schematics/bad_trace_v1.jpeg add pic add pic 2118197c1e2cab02a4a0c4b6381e9d7946ff4f12 move bugs to md.
- Normal -0.0208841 -0.0914064 -0.995595 facet normal -9.989484e-01.
- Resistors **Corrected:** Updated C5.
- Vertical_space/7; row_3 = row_2.