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Cap.STL Executable file View File 3D Printing/Cases/Eurorack Modular Case/EuroRack_Case_End_Female.png Executable file View File 3D Printing/Cases/Eurorack Modular Case/EuroRack_Case_End_Male.stl Executable file View File 3D Printing/Pot_Knobs/FS_PotiKnob_d6D12h9.stl Executable file View File 3D Printing/Jigs/eurorack_test_jig_150mm.stl Executable file View File 3D Printing/Panels/HOLD PORTAL.png | Bin 0 -> 69774 bytes Images/precadsr-panel-art.png | Bin 0 -> 11692 bytes { "board": { Add a horizontal wall (across the panel module v_wall(h, l, wall_thickness); Align panel to integer pseudo-origin, remove testing text, decrease title label font size to 9mm and align it precisely for repeatability b11a8d31874f2e074879a668b4f6eb5f32915bd6 Change transistor footprint to inline_wide, fix DRC ground plane 5e32fb4fc0953f2a10f8dc9cf7a0a3653bcbf4f2 @circuitlocution.com created pull request 'Finish schematic, add PDF' (#2) from schematic into main v1 Final tweaks, version submitted to JLCPCB on 20240124 63579cf959 Add notes about UX component wiring 55ee65a5e9 Checkpoint after re-centering sliders, before removing redundant LED resistors next to transistors to save on panel wires More traces and vias, and this is good practice, but ho-dang what a mess romps with traces, vias, and net links 06eccf7d9c added the once through idea with commentary by Correcting changed filename in .prl Correcting changed filename in .prl gets jiggy with PCB locator, 14 Pins (http://www.molex.com/pdm_docs/sd/908140004_sd.pdf), generated with kicad-footprint-generator Molex Picoflex Ribbon-Cable Connectors, 90814-0014, 14 Pins (http://www.molex.com/pdm_docs/sd/903250004_sd.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py QFN, 48 Pin (https://www.jedec.org/standards-documents/docs/mo-142-d variation BB), generated with kicad-footprint-generator Soldered wire connection with feed through strain relief, for a single 1.5 mm² wire, reinforced insulation, conductor diameter 1.7mm, outer diameter 1.5mm.

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