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P2; ValeurCmp = Analog; IdModule = Socket_Arduino_Nano:1pin_Nano; EndCmp BeginCmp TimeStamp = /551D9414; Reference = P4; ValeurCmp = Digital; IdModule = Socket_Arduino_Nano:1pin_Nano; EndCmp BeginCmp TimeStamp = /551D9380; Reference = P1; ValeurCmp = CONN_1; IdModule = Socket_Arduino_Nano:1pin_Nano; EndCmp Hardware/PCB/precadsr/precadsr.kicad_pcb Normal file Unescape Hardware/PCB/precadsr/ao_tht.pretty/Perf_Board_Hole.kicad_mod Normal file Unescape Hardware/Panel/precadsr-panel/precadsr-panel.pretty/precadsr-panel-art.kicad_mod Normal file Unescape Drill report for precadsr-panel.kicad_pcb Created on Tue Mar 5 20:19:51 2024 Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains T1 3.200mm 0.1260" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole) T3 7.000mm 0.2756" (6 holes) T4 10.000mm 0.3937" (4 holes) T5 15.200mm 0.5984" (1 hole Total plated holes count 16 ============================================================= Total unplated holes count 16 Not plated through holes: ============================================================= From a22bca6d29ddc0a54597dab4d11ad9ab7e48e3c6 Mon Sep 17 00:00:00 2001 Subject: [PATCH 08/13] More notes move bugs to md file to be able to add picture 5082711a98 Add a front-panel PCB "net_color_mode": 1, "opacity": { More tweaks after pro review "extra_units": "error", "global_label_dangling": "warning", "hier_label_mismatch": "error", "label_dangling": "error", "lib_symbol_issues": "warning", More tweaks after pro review More tweaks after pro review "clearance": 0.2, "diff_pair_gap": 0.25, "diff_pair_via_gap": 0.25, "diff_pair_width": 0.2, "line_style": 0, "microvia_diameter": 0.3, "microvia_drill": 0.1, "name": "Default", "pcb_color": "rgba(0, 0, 0, 0.000)", "schematic_color": "rgba(0, 0, 0, 0.000)", "track_width.

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