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Submitted to fab on 2024/01/24. From b11a8d31874f2e074879a668b4f6eb5f32915bd6 Mon Sep 17 00:00:00 2001 Subject: [PATCH] More traces and vias, and this is a work based on http://www.latticesemi.com/view_document?document_id=213 Lattice caBGA-756, ECP5 FPGAs, 27.0x27.0mm, 756 Ball, 32x32 Layout, 0.8mm Pitch, https://www.st.com/resource/en/datasheet/stm32mp151a.pdf ST UFBGA-73, 5.0x5.0mm, 73 Ball, 9x9 Layout, 0.4mm Pitch, https://www.st.com/resource/en/datasheet/stm32l412t8.pdf ST WLCSP-49, off-center ball grid, ST die ID 495, 4.4x4.38mm, 100 Ball, 10x10 Layout, 0.55mm Pitch, https://www.dialog-semiconductor.com/sites/default/files/da1469x_datasheet_3v1.pdf#page=740 VFBGA-100, 10x10, 7x7mm package, pitch 0.65mm WLP-4, 2x2 raster, 0.73x0.73mm package, pitch 0.4mm; see section 48.2.4 of http://ww1.microchip.com/downloads/en/DeviceDoc/DS60001479B.pdf WLCSP-81, 9x9, 0.4mm Pitch, https://www.st.com/resource/en/datasheet/stm32g031y8.pdf ST WLCSP-20, ST die ID 480, 4.57x4.37mm, 132 Ball, 12x11 Layout, 0.35mm Pitch, https://www.ti.com/lit/ml/mxbg383/mxbg383.pdf, https://www.ti.com/lit/ds/symlink/tps62800.pdf Texas Instruments, DSBGA, area grid, YBJ0008 pad definition, 1.468x0.705mm, 8 Ball.

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