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DFN 0.65P dual flag WDFN-8 1EP 2.2X2.0 0.5P WDFN, 8 Pin (https://www.infineon.com/cms/en/product/packages/PG-DSO/PG-DSO-8-27), generated with kicad-footprint-generator JST SH series connector, LY20-40P-DLT1, 20 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ038187.pdf), generated with kicad-footprint-generator Molex Mini-Fit Jr. Power Connectors, 42820-32XX, With thermal vias in pads, 7 Pins per row (http://suddendocs.samtec.com/prints/lshm-1xx-xx.x-x-dv-a-x-x-tr-footprint.pdf), generated with kicad-footprint-generator Soldered wire connection with double feed through strain relief, for a clock on the larger board underneath the smaller board. #Kicad 7 # 2-layer, 1oz copper condition "A.Type == 'pad' && A.Fabrication_Property == 'Castellated pad'" condition "A.Net != B.Net" (condition "A.Type == 'track' && B.Type == A.Type && A.Net == B.Net" (condition "A.Type == 'pad' && (B.Type == 'text' || B.Type == 'track'" (condition "A.Type == 'track'")) # This would override board outline.

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