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BackPin (https://www.ti.com/lit/ml/mmsf022/mmsf022.pdf TO-PMOD-11 11-pin switching regulator package, http://www.ti.com/lit/ml/mmsf025/mmsf025.pdf Vishay PowerPAK SC70 single transistor package http://www.vishay.com/docs/70487/70487.pdf powerpak sc70 sc-70 dual Vishay PowerPAK 1212-8 Single Zetex, SMD, 8 pin DIP socket A-004 4 Knobs Screws, nuts, and spacers (see build notes) 1 SIP socket, 2.54 mm, 1x7 Pin socket, 2.54 mm, 1x10 Pin header, 2.54 mm, 1x10 Pin socket, 2.54 mm, 1x10 Pin socket, 2.54 mm, 1x2 (see [build notes](build.md | | | | | | | | 2 Smaller cap (476nF?) for C1 Ceramic 104s for C10, C14, might be fine, might introduce intermittents - Don't put R8 so close to R26 D36/R47 too close Testing before powering up: Clock In - ~27K to U3-8? No, transistors maybe activate? - Clock rate goes down when resistance goes up, opposite to expectation. Glide fix Notes from MK's PCB livestream - avoid non-circular holes in footprints whenever possible; some fabs charge more for ovals PCB layout: [front](Docs/precadsr_layout_front.pdf), [back](Docs/precadsr_layout_back.pdf * [How to use](Docs/use.md 96f746fa2d Final tweaks, version submitted to JLCPCB on 20240124 63579cf959 Add notes about wiring SW15 cross-board facet normal -0.590348 0.804076 0.0703604 facet normal 0.109686 -0.552315 -0.826388 vertex 0.4 -2.96144 10.597 vertex 0.4 3.26571 14.9643 vertex -1.45059 3.07081 15.6068 vertex -0.4 3.26571 14.9643 vertex -1.45059 3.07081 15.6068 vertex 1.31069 3.16429 6.59 vertex 2.56201 -2.21206 6.59 facet normal -8.091787e-01 -1.313994e-03 -5.875612e-01 facet normal 0.900717 0.422905 0.0992962.
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