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Removed below exposed pad; keepout area marked (Package see: https://store.invensense.com/datasheets/invensense/MPU-6050_DataSheet_V3%204.pdf; See also https://www.invensense.com/wp-content/uploads/2015/02/InvenSense-MEMS-Handling.pdf 24-Lead Plastic DFN (2mm x 2mm) (see Linear Technology 05081733_A_DF12.pdf DFN12, 4x4, 0.65P; CASE 506CE (see ON Semiconductor 506BU.PDF 8-Lead Plastic DFN (4mm x 3mm) (see Linear Technology DFN_16_05-08-1709.pdf DHC Package; 18-Lead Plastic DFN (3mm x 3mm) (see Linear Technology 05081707_A_DHD16.pdf DH Package; 16-Lead Plastic DFN (2mm x 2mm) 0.40mm pitch DDB Package; 12-Lead Plastic Micro Small Outline (ST)-4.4 mm Body [TQFP] (see Microchip Packaging Specification 00000049CH.pdf SC-74, 6 Pin (https://www.ti.com/lit/ds/symlink/sn74auc1g04.pdf#page=24), Solder Mask Defined VSON, 8 Pin (https://ams.com/documents/20143/36005/AS7341_DS000504_3-00.pdf/#page=63 LGA, 8 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/mic23050.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py PowerPAK 1212-8 Dual (https://www.vishay.com/docs/71656/ppak12128.pdf, https://www.vishay.com/docs/72598/72598.pdf PowerPAK 1212-8 Single (https://www.vishay.com/docs/71656/ppak12128.pdf, https://www.vishay.com/docs/72597/72597.pdf.

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