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Href="https://gitea.circuitlocution.com/synth_mages/synth_tools/commit/122134fc8e1c73b6bb86552323cca038dd4b5107">122134fc8e1c73b6bb86552323cca038dd4b5107 Binary files /dev/null and b/sr1_full.png differ aac0a4a5b4 Notes from MK's PCB livestream # Format documentation: https://kicad.org/help/file-formats/ # Netlist files (exported from Eeschema *.csv *.lck ########################## # Additional ignored # KiCad backups folders temp_* # Compressed files *.zip # Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: T5 15.200mm 0.5984" (1 hole Total plated holes unplated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes.

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