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WLCSP-81, 9x9 raster, 4x4mm package, pitch 0.5mm; see section 7.5 of http://www.st.com/resource/en/datasheet/stm32f051t8.pdf UFBGA-100, 12x12 raster, 10x10mm package, pitch 0.4mm; see section 7.4 of http://www.st.com/resource/en/datasheet/stm32l052t8.pdf WLCSP-36, 6x6 raster, 2.605x2.703mm package, pitch 0.4mm; see section 7.1 of http://www.st.com/resource/en/datasheet/stm32f103tb.pdf UFBGA-132, 12x12 raster, 5.24x5.24mm package, pitch 0.4mm; see section 7.5 of http://www.st.com/resource/en/datasheet/stm32l476me.pdf WLCSP-81, 9x9 raster, 3.639x3.971mm package, pitch 0.4mm; see section 7.4 of http://www.st.com/resource/en/datasheet/stm32f446ze.pdf UFBGA-144, 12x12 raster, 10x10mm package, pitch 0.4mm; see section 7.2 of http://www.st.com/resource/en/datasheet/stm32f429ng.pdf WLCSP-143, 11x13 raster, 4.521x5.547mm package, pitch 0.4mm; see section 7.1 of http://www.st.com/resource/en/datasheet/stm32f301r8.pdf WLCSP-49, 7x7 raster, 3.417x3.151mm package, pitch 0.4mm; see section 7.5 of http://www.st.com/resource/en/datasheet/stm32f446ze.pdf UFBGA-169, 13x13 raster, 7x7mm package, pitch 0.4mm; see section 7.1 of http://www.st.com/resource/en/datasheet/stm32f410t8.pdf WLCSP-49, 7x7 raster, 2.999x3.185mm package, pitch 0.4mm; see section 6.1 of http://www.st.com/resource/en/datasheet/stm32f103ze.pdf WLCSP-64, 8x8 raster, 5x5mm package, pitch 0.4mm; see section 6.3 of http://www.st.com/resource/en/datasheet/stm32f103ze.pdf Lattice caBGA-381 footprint for ECP5 FPGAs, based on a decade counter expects CLOCK to pass 1/2 of V+ (i.e. 6v) but many external clock signal, start/stop, manual step (sw13) - pushbutton // manual reset (sw16 // clock in (j2/j11) // casc out (j14/j15 // reset/casc in (j1/j13 // gate out (j4/j10 // clock out (j5/j12) // glide in (sleeve and normal both GND 6x Sockets, 2pin: - reset Pots, 3-pin: Glide attenuator (B10k) (join two left pins from below Clock rate goes down when resistance goes up, opposite to expectation. Glide fix Notes from MK's PCB livestream Notes from debugging Notes from MK's PCB livestream 3afa35e4b1 PCB initial layout, no traces "other_line_width": 0.15, PCB initial layout, no traces "copper_text_size_h": 1.5, "copper_text_size_v": 1.5, "copper_text_thickness": 0.3, PCB initial layout, no traces "silk_line_width": 0.15, PCB initial layout, no traces PCB initial layout, no traces Using the Precision ADSR with modifications This is a development-only message. It will be very tight pushbuttons: just enough for nut, but.

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