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BackI Know Hardware/PCB/precadsr/Kosmo_panel.pretty/Kosmo_Jack_Hole.kicad_mod Normal file Unescape Schematics/SynthMages.pretty/6.3mm_NPTH_MAXJLCPCB.kicad_mod Normal file View File Hardware/PCB/precadsr_Gerbers/precadsr-F_Mask.gbr Normal file View File RadioShaek2Board.diy Executable file View File 3D Printing/Pot_Knobs/potknob_parametric.scad Executable file View File Images/precadsr-panel.png Normal file Unescape BeginCmp TimeStamp = /551D9414; Reference = P2; ValeurCmp = Analog; IdModule = Socket_Arduino_Nano:1pin_Nano; EndCmp Hardware/PCB/precadsr/precadsr.kicad_pcb Normal file View File # For PCBs designed using KiCad: https://www.kicad.org/ # Format documentation: http://kicad-pcb.org/help/file-formats/ # Temporary files fp-info-cache # Autorouter files (exported from Eeschema # Autorouter files (exported from Eeschema) *.net # Autorouter files (exported from Eeschema *.csv *.lck ########################## # Additional ignored # KiCad backups folders *-backups # Compressed files *.zip # Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes are merged with plated holes count 16 Not plated through holes are merged with plated holes count 16 Not plated through holes: merged pull request 'pcb_finalization' (#1) from bugfix/10hp into main ... Add jlc constraints DRC; replace order number text 613d1b6f7ef8de710893bbeb40d56c8d26d50247 @circuitlocution.com.
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