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BackAnd b/Panels/Font files/futura light bt.ttf | Bin 0 -> 10174 bytes .../PRISMATIC SPHERE.png | Bin 0 -> 676484 bytes 3D Printing/Panels/FIREBALL VCO.png create mode 100644 Images/IMG_6771.JPG create mode 100644 3D Printing/Pot_Knobs/potentiometre_v3.stl create mode 100644 Hardware/PCB/precadsr_Gerbers/precadsr-F_Paste.gbr create mode 100644 Hardware/PCB/precadsr/ao_tht.pretty/Push_button_A-5050.kicad_mod create mode 100644 Panels/futura light bt.ttf | Bin 0 -> 4233424 bytes create mode 100644 Hardware/Panel/precadsr_panel_al/precadsr_panel_al.pro delete mode 100644 Hardware/Panel/precadsr-panel/precadsr-panel.kicad_sch "Pots, switches, misc" plated through holes are merged with plated holes Total unplated holes count 16 Not plated through holes are merged with plated holes count 16 Not plated through holes are merged with plated holes count 16 Not plated through holes are merged with plated holes Total unplated holes count 16 Not plated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) T5 15.200mm 0.5984" (1 hole Total plated holes unplated through holes: unplated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole) Total plated holes count 0 Minor layout tweaks From cd915e24c94d463c67b0b011c09a1ed6f99bb0bf Mon Sep 17 00:00:00 2001 Subject: [PATCH 06/18] tracks the ratsnest and compactifies the power subsystem footprint "Perfboard_2x12" (version 20221018) (generator pcbnew footprint "SOCKET_2_PIN_Header" (version 20211014) (generator pcbnew Show-stopping bugs needing bodges: Errant connection between R25 and R1. This needs to be +1mm between legs -- Don't put R8 so close to R26 -- D36/R47 too close Testing before powering up: Clock In - ~27K to U3-8? No, transistors maybe activate? - Clock In - diode to U2-3 - Clock Rate - variable resist +6k between U2-8 and U2-9 Reset Sw - when pressed, short +12V and Reset In socket Reset Socket to U3-3.