Labels Milestones
Back1/2] Fix rail clearance issues, make all power traces large "rules": { PCB initial layout, no traces "min_copper_edge_clearance": 0.0, PCB initial layout, no traces PCB initial layout, no traces }, More tweaks after pro review "multiple_net_names": "warning", "net_not_bus_member": "warning", "no_connect_connected": "warning", "no_connect_dangling": "warning", "pin_not_connected": "error", "pin_not_driven": "error", "pin_to_pin": "warning", "power_pin_not_driven": "error", "similar_labels": "warning", More tweaks.
- -3.44477 9.2078 1.51264 vertex -3.47906 -9.35243.
- Vertex -9.8813 2.36142 0 vertex.
- -6.451849e-01 3.340831e-04 facet normal 0.552085 0.110591 -0.826421 vertex.
- -0.0938358 -0.952717 0.289008 vertex -8.97218 0 4.79464.
- LFCSP, 40 Pin (http://www.ti.com/lit/ds/symlink/msp430g2755.pdf#page=70 JEDEC MO-220.