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C3 and C4 could use fewer caps that way 7022ad9ddb couple more minor clearance tweaks Add ground fills, fix some clearance issues, make all power traces large "rules": { PCB initial layout, no traces PCB initial layout, no traces "silk_line_width": 0.15, PCB initial layout, no traces "min_copper_edge_clearance": 0.0, PCB initial layout, no traces PCB initial layout, no traces One SPST switch per step, to set number of pins: 15; pin pitch: 5.08mm.

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