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6.45265 -0.325107 19.4867 vertex 2.6794 -1.7206 19.8418 facet normal 8.050200e-02 -7.673375e-03 -9.967249e-01 facet normal -0.164775 -0.491639 0.855067 vertex -7.15425 0.422769 6.96188 vertex 5.25893 -4.75047 6.95295 vertex -4.9518 -5.2649 6.88859 facet normal 4.866829e-001 -8.343584e-001 2.588163e-001 facet normal -0.573973 -0.597991 0.55943 vertex 5.74517 -4.54413 7.2866 facet normal -2.554371e-001 -4.462929e-001 8.576564e-001 vertex 4.750911e-002 -6.030936e+000 2.492316e+001 facet normal 4.844567e-01 2.942353e-03 8.748103e-01 vertex -1.092005e+02 9.725134e+01 6.037139e+00 facet normal -0.32036 0.220665 0.921236 facet normal 5.853797e-004 0.000000e+000 -9.999998e-001 facet normal 1.128946e-13 -1.000000e+00 -7.310141e-15 facet normal -0.243743 -0.188053 0.951433 vertex -0.221399 7.2243 6.88859 facet normal 0.462456 0.449684 0.764146 vertex -6.81829 0.589577 7.19149 vertex 4.29047 5.40904 7.37319 vertex -4.27288 5.22414 7.35649 facet normal -0.706052 -0.0555714 0.705976 facet normal 0.95132 0.288583 0.108209 vertex -3.18104 -4.87024 21.335 facet normal 0.749604 0.288937 0.59549 vertex 5.40021 -4.41978 7.20613 vertex -0.589577 -6.81829 7.19149 vertex 4.29047 -5.40904 7.37319 facet normal 0.346108 0.295597 0.890411 vertex 5.56465 -0.378418 18.9636 facet normal 0.468624 0.876745 0.108209 vertex 5.20733 -2.5504 21.335 facet normal -0.977459 -0.186424 0.0990923 facet normal 0.012671 -0.705364 0.708732 vertex -7.28282 0.821781 7.24568 facet normal -2.880153e-004 -5.040268e-004 -9.999998e-001 ## Documentation: * [Schematic](Docs/precadsr.pdf) * PCB layout: [front](Docs/precadsr_layout_front.pdf), [back](Docs/precadsr_layout_back.pdf * [How to use](Docs/use.md 96f746fa2d Final tweaks, version submitted to JLCPCB on 20240124 v1.0 Add CV in to pause the clock and keeps current gate open whenever the voltage exceeds a certain threshold (perhaps useful.

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