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BackFile Hardware/PCB/precadsr/sym-lib-table Normal file Unescape Drill report for precadsr-panel.kicad_pcb Created on Tue Mar 5 20:19:51 2024 Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains T1 3.200mm 0.1260" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole) Total plated holes Total unplated holes count 16 Not plated through holes are merged with plated holes count 16 Not plated through holes are merged with plated holes unplated through holes: unplated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole) T3 7.000mm 0.2756" (6 holes) T4 10.000mm 0.3937" (4 holes T5 15.200mm 0.5984" (1 hole Total plated holes unplated through holes: ============================================================= From a22bca6d29ddc0a54597dab4d11ad9ab7e48e3c6 Mon Sep 17 00:00:00 2001 Subject: [PATCH] Fix rail clearance issues, make all power traces large Add ground fills, fix some clearance issues, add PCB slot, more options.
- Normal -0.166294 0.21962 0.961308 vertex -5.04394 -5.04394.
- (end 1.88 -0.98 (end -1.88 -0.98 (end.
- 0.367744 0.923212 facet normal 0.449666.
- GND-vias (https://ww2.minicircuits.com/pcb/98-pl035.pdf Footprint for Mini-Circuits case MMM168 (https://ww2.minicircuits.com/case_style/MMM168.pdf.
- 0.767777 -0.634425 0.0895734 facet normal -0.0974021.