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FF900 FFG900 FFV900 FF901 FFG901 FFV901 Artix-7, Kintex-7 and Zynq-7000 BGA, 34x34 grid, 35x35mm package, 1mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=278, https://www.xilinx.com/support/documentation/user_guides/ug865-Zynq-7000-Pkg-Pinout.pdf#page=92, NSMD pad definition Appendix A BGA 324 0.8 GateMate FPGA Maxim WLP-12, W121H2+1, 2.008x1.608mm, 12 Ball, 4x3 Layout, 0.4mm Pitch, https://pdfserv.maximintegrated.com/package_dwgs/21-100489.PDF WLCSP-25, 5x5 raster, 2.097x2.493mm package, pitch 0.4mm; see section 7.1 of http://www.st.com/resource/en/datasheet/stm32f103tb.pdf LFBGA-144, 12x12 raster, 7x7mm package, pitch 0.4mm; see section 7.7 of http://www.st.com/resource/en/datasheet/DM00330506.pdf WLCSP-100, 10x10 raster, 4.201x4.663mm package, pitch 0.65mm UFBGA-32, 6x6, 4x4mm package, pitch 0.5mm (http://www.analog.com/media/en/package-pcb-resources/package/56702234806764cp_24_3.pdf, http://www.analog.com/media/en/technical-documentation/data-sheets/ADL5801.pdf LFCSP VQ, 48 pin, exposed pad: 4.5x8.1mm, (https://www.infineon.com/cms/en/product/packages/PG-DSO/PG-DSO-12-9/ Infineon PG-DSO 12 pin, exposed pad: 4.5x8.1mm, with thermal pad TSSOP HTSSOP 0.65 thermal pad TQFP64 7x7, 0.4P CASE 932BH (see ON Semiconductor 122BS.PDF PQFP, 100 Pin (http://www.microsemi.com/index.php?option=com_docman&task=doc_download&gid=131095), generated.

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