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Back# Compressed files *.zip # Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains T1 3.200mm 0.1260" (4 holes) T5 15.200mm 0.5984" (1 hole) Total plated holes count 0 Hardware/Panel/precadsr-panel-Gerbers/precadsr-panel-CmtUser.gbr Normal file Unescape module railWithHoles(height) { difference(){ color([.1,.1,.1]) panel(width); // lower h-rib reinforcer Latest commits for file PSU/psu.diy Add PSU PSU/PSU.md | 5 create mode 100644 Fireball/Fireball.kicad_prl create mode 100644 Hardware/PCB/precadsr/ao_tht.pretty/C_Rect_L7.2mm_W2.5mm_P5.00mm_FKS2_FKP2_MKS2_MKP2.kicad_mod create mode 100644 Hardware/PCB/precadsr/ao_tht.pretty/R_Axial_DIN0207_L6.3mm_D2.5mm_P7.62mm_Horizontal.kicad_mod create mode 100644 Panels/luther_triangle_vco_quentin_v3_only_art.stl create mode 100644 README.md create mode 100644 Hardware/PCB/precadsr/ao_tht.pretty/Wall_wart_A-4118.kicad_mod delete mode 100644 Images/PXL_20210831_002553634.jpg Latest commits for file Images/IMG_6771.JPG From fdd5744d7827ea7bf3ef1dd3cdfaa880615e1567.
- -0.161939 -0.264267 0.950757 vertex 4.06086 0.665604.
- 8.032235e-01 vertex -1.048853e+02 9.695134e+01.