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BackAdopt github .gitignore file # Temporary files *.000 *.bak *.bck *.kicad_pcb-bak *.kicad_sch-bak *-backups */fp-info-cache *.kicad_prl *.sch-bak *~ _autosave-* *.tmp *-save.pro *-save.kicad_pcb fp-info-cache *.lck # Netlist files (exported from Eeschema # Autorouter files (exported from Eeschema *.csv *.lck ########################## # Additional ignored # KiCad backups folders *-backups # Compressed files *.zip # Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) (with 4 slots T2 5.000mm 0.1969" (1 hole Total plated holes Total unplated holes count 16 Not plated through.
- -0.286341 -0.118613 0.950757 facet normal 0.479377 0.871976 0.0992747.
- 1.130036e-04 vertex -9.358794e+01 1.050106e+02 4.255000e+01 facet normal -4.648458e-001.
- Size 81.3x9.8mm^2, drill diamater 1.3mm.
- Normal 0.991507 -0.0942884 0.0895734 facet normal -0.0096566 0.0980067.