Drill report for precadsr-panel.kicad_pcb
Created on Tue Mar  5 20:19:51 2024

Copper Layer Stackup:
    =============================================================
    L1 :  F.Cu                      front
    L2 :  B.Cu                      back


Drill file 'precadsr-panel.drl' contains
    plated through holes:
    =============================================================
    T1  3.200mm  0.1260"  (4 holes)  (with 4 slots)
    T2  5.000mm  0.1969"  (1 hole)
    T3  7.000mm  0.2756"  (6 holes)
    T4  10.000mm  0.3937"  (4 holes)
    T5  15.200mm  0.5984"  (1 hole)

    Total plated holes count 16


Not plated through holes are merged with plated holes
    unplated through holes:
    =============================================================

    Total unplated holes count 0