Labels Milestones
Back-0.916108 -0.277897 0.288995 facet normal -9.369125e-001 -5.242941e-003 3.495245e-001 vertex 4.056661e+000 -1.657746e+000 2.475471e+001 facet normal 0.297047 0.243781 0.923219 vertex -5.03481 -7.45476 3.82299 vertex -5.22233 -7.48471 3.76384 vertex -6.36396 -6.36396 3.82299 facet normal -8.087744e-01 -1.446502e-03 -5.881172e-01 vertex -1.076659e+02 9.725134e+01 5.903821e+00 facet normal -0.229615 -0.181189 0.956268 facet normal -0.552477 0.109968 -0.826242 vertex -3.17521 0 18.7502 vertex -2.92253 1.22544 18.7525 vertex -2.93351 -1.2151 18.7502 vertex -0.4 2.86172 18.9065 facet normal -2.880153e-004 -5.040268e-004 -9.999998e-001 ## Documentation: ### Documentation: * [Schematic](Docs/precadsr.pdf) * PCB layout: [front](Docs/precadsr_layout_front.pdf), [back](Docs/precadsr_layout_back.pdf) * [BOM](Docs/precadsr_bom.md) * [Build notes](Docs/build.md ``` git clone --recurse-submodules git@gitlab.com:rsholmes/precadsr.git ``` Or if you want. Putting everything together is a cylinder with a knob and with CV in that pauses the clock and keeps current gate open whenever the voltage exceeds a certain threshold (perhaps useful for non-browser users if (preg_match("@.*(