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BackPrecadsr/Docs/build.md 65 lines # Temporary files *.000 *.bak *.bck *.kicad_pcb-bak *.kicad_sch-bak *.kicad_prl *.kicad_pro *.rules *.sch-bak *~ _autosave-* *.tmp *-save.pro *-save.kicad_pcb fp-info-cache # Netlist files (exported from Eeschema *.csv *.lck ########################## # Additional ignored # KiCad backups folders *-backups # Compressed files *.zip # Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes are merged with plated holes count 0 Hardware/Panel/precadsr-panel-Gerbers/precadsr-panel-CmtUser.gbr Normal file View File Panels/title_test_36.stl Normal file Unescape 3D Printing/Pot_Knobs/scaled_french_pot.mix | Bin 0 -> 406884 bytes ...uther_triangle_vco_quentin_v3_only_art.stl | Bin 0 -> 104908 bytes Panels/title_test.scad | 27 Panels/title_test.stl | Bin 0 -> 15005 bytes Panels/FireballSpellVertVerySmall.png | Bin 0 -> 328607 bytes Images/PXL_20210831_001017829.jpg | Bin 0 -> 146728 bytes Images/IMG_6771.JPG | Bin 0 -> 136810 bytes.
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