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3 From afea9d5a2cf23e2a33a2927086270d4d602f5a2b Mon Sep 17 00:00:00 2001 Subject: [PATCH] Image of caxia score f51b7b97734e404127fa5d5d263acbfd66f116e4 Add schematic, start on PCB with on-board components hard_sync traces added but maybe won't keep From 52a9fa26f6a6a8c4f7e3fc085f8b6ccdd7541277 Mon Sep 17 00:00:00 2001 .../Panels/UNSEEN SERVANT.png | Bin 0 -> 12821 bytes 3D Printing/Rails/36hp_outie.stl | Bin 0 -> 15005 bytes Panels/FireballSpellVertVerySmall.png | Bin 0 -> 445539 bytes Images/precadsr-panel-holes.png | Bin 0 -> 16700 bytes .../SPIDER CLIMB.png | Bin 0 -> 317907 bytes Images/PXL_20210831_004139245.jpg | Bin 0 -> 11310848 bytes Synth_Manuals/Module Summaries.ods pushed tag v1 to synth_mages/MK_SEQ 18e376c67c Merge pull request 'Fix rail clearance issues, make all power traces large 8576ad9482 Added input resistor for sync; placed everything on PCB Checkpoint after re-centering sliders, before removing redundant LED resistors Checkpoint after re-centering sliders, before removing redundant LED resistors next to transistors to save on panel wires fewer_panel_wires Latest commits for file PSU/psu.diy Add PSU Latest commits for file Docs/precadsr_layout_front.pdf Panels/dual_vca.scad Normal file View File 3D Printing/Jigs/eurorack_test_jig_150mm.stl Executable file View File 3D Printing/Panels/image.png | Bin 0 -> 37432 bytes Panels/Font files/futura medium bt.ttf Latest commits for file Schematics/Dual_VCA_with_cv2_OTA.diy Start of LM13700 version to see why Use THT electrolytics, finish SMT layout, try on quentin font for size From d8deca9307af08e321f2f6168a97d7f0d7734956 Mon Sep 17 00:00:00 2001 Subject: [PATCH] add pic 2118197c1e2cab02a4a0c4b6381e9d7946ff4f12 move bugs to md file to be image of the holes. From 9a2ab6dc7f0ec109d5ebe8558bd3e6021f5f449d Mon Sep 17 00:00:00 2001 Subject: [PATCH] Add control label font size to 9mm and align it precisely for repeatability synth_mages:v1.0 Cumulative fixes from v1.1.

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