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1.27mm; (see Texas Instruments DSBGA BGA YZR0009 Texas Instruments, DSBGA, 0.9x1.9mm, 8 bump 2x4 (perimeter) array, NSMD pad definition Appendix A Artix-7 BGA, 26x26 grid, 27x27mm package, 1mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=298, https://www.xilinx.com/support/documentation/user_guides/ug865-Zynq-7000-Pkg-Pinout.pdf#page=94, NSMD pad definition Appendix A Artix-7 BGA, 19x19 grid, 10x10mm package, 0.5mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=266, NSMD pad definition (http://www.ti.com/lit/ds/symlink/txb0102.pdf, http://www.ti.com/lit/an/snva009ag/snva009ag.pdf Texas Instruments, DSBGA, area grid, YZR pad definition Appendix A BGA 900 1 FB900 FBG900 FBV900 Kintex-7 and Zynq-7000 BGA, 15x15 grid, 13x13mm package, pitch 0.8mm; see section 7.2 of http://www.st.com/resource/en/datasheet/stm32f429ng.pdf WLCSP-143, 11x13 raster, 4.539x5.849mm package, pitch 0.8mm; see section 7.4 of http://www.st.com/resource/en/datasheet/stm32l476me.pdf WLCSP-81, 9x9 raster, 3.639x3.971mm package, pitch 0.5mm; see section 7.6 of http://www.st.com/resource/en/datasheet/stm32f446ze.pdf UFBGA-169, 13x13 raster, 7x7mm package, pitch 0.4mm; see section 7.5 of http://www.st.com/resource/en/datasheet/stm32f303r8.pdf WLCSP-49, 7x7 raster, 3.417x3.151mm package, pitch 0.4mm; see section 7.5 of http://www.st.com/resource/en/datasheet/stm32l152zc.pdf UFBGA 132 Pins, 0.5mm Pitch, https://www.st.com/resource/en/datasheet/stm32wl54jc.pdf ST UFBGA-121, 6.0x6.0mm, 121 Ball, 11x11 Layout, 0.5mm Pitch, http://www.ti.com/lit/ds/symlink/ts3a24159.pdf Texas Instruments, DSBGA, 3.0x1.9x0.625mm, 28 ball 7x4 area grid, NSMD pad definition Appendix A BGA 900 1 FF900 FFG900 FFV900 FF901 FFG901 FFV901 Artix-7, Kintex-7 and Zynq-7000 BGA, 22x22 grid, 19x19mm package, 0.8mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug865-Zynq-7000-Pkg-Pinout.pdf#page=77, NSMD pad definition Appendix A BGA 238 0.5 CP236 CPG236 Artix-7 BGA, 16x16 grid, 17x17mm package, 0.8mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug865-Zynq-7000-Pkg-Pinout.pdf#page=79, NSMD pad definition (http://www.ti.com/lit/ds/symlink/bq51050b.pdf, http://www.ti.com/lit/an/snva009ag/snva009ag.pdf Texas Instruments, NDQ, 5 pin (https://www.ti.com/lit/ml/mmsf022/mmsf022.pdf TO-PMOD-11 11-pin switching regulator package, http://www.ti.com/lit/ml/mmsf025/mmsf025.pdf Vishay PowerPAK 1212-8 Single (https://www.vishay.com/docs/71656/ppak12128.pdf, https://www.vishay.com/docs/72597/72597.pdf Vishay PowerPAK 1212-8 Single Zetex, SMD, 8 pin DIP socket | | | | D3, D4, D5, D8, D9, D10 | 8 pin DIP socket | | R30 | 1 | 2_pin_Molex_header | 2 | 1nF | Unpolarized capacitor | | Tayda | A-1847 | | J6 | 1 nF | Unpolarized capacitor | | Tayda | A-159 | | Tayda | A-1847 | | | Tayda | A-553 | | C2 | 1 | SW_SPDT | SPDT miniature toggle switch ON-ON | | | | | | | | | S3 | 1 | 2_pin_Molex_header | 2 | 1N5817 | Schottky Barrier Rectifier Diode, DO-41 D3, D4, D5, D8, D9, D10 | 8 "active_layer_preset": "All Layers", "active_layer_preset": "All Copper Layers", re-re-remove the mysterious extra trace re-re-remove the mysterious extra trace 5040873587dbb57684343269abab88d35cf7124b Update Schematics/schematic_bugs_v1.md Clock POT is too small; need more than fifty percent.

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