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BackCase/EuroRack_Case_26.stl Executable file Unescape Hardware/Panel/precadsr-panel-Gerbers/precadsr-panel-SilkTop.gto Normal file View File Hardware/PCB/precadsr/sym-lib-table Normal file Unescape Hardware/PCB/precadsr/precadsr.cmp Normal file Unescape Drill report for precadsr-panel.kicad_pcb Created on Tue Mar 5 20:19:51 2024 Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) T5 15.200mm 0.5984" (1 hole T3 7.000mm 0.2756" (6 holes T4 10.000mm 0.3937" (4 holes T5 15.200mm 0.5984" (1 hole Total plated holes count 16 Not plated through holes are merged with plated holes Total unplated holes count 16 ============================================================= Total unplated holes count 0 Hardware/Panel/precadsr-panel-Gerbers/precadsr-panel-CmtUser.gbr Normal file Unescape Hardware/PCB/precadsr/ao_tht.pretty/Potentiometer_Alps_RK163_Single_Horizontal.kicad_mod Normal file View File Images/IMG_6777.JPG Normal file View File b404e3f9c5 Update.
- Board or similar size.
- Vertex 6.58293 0.759029 7.7465 facet.
- Normal -0.262761 0.491592 0.830237 vertex -5.04122 7.99026.
- 5.10253 6.1679 19.9507 vertex 5.86835 7.35868 20.0916.