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BackOatmeal initial 2015-04-27 01:31:45 -07:00 From cb3a50e19a42a9ab425057cfa1f9427c1c21d019 Mon Sep 17 00:00:00 2001 Subject: [PATCH] Update luther's layout Update luther's layout Drill report for precadsr-panel.kicad_pcb Created on Tue Mar 5 20:19:51 2024 Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains T1 3.200mm 0.1260" (4 holes) T5 15.200mm 0.5984" (1 hole Total plated holes count 16 Not plated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole) Total plated holes Total unplated holes count 16 Not plated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) T5 15.200mm 0.5984" (1 hole) T3 7.000mm 0.2756" (6 holes T4 10.000mm 0.3937" (4 holes) T5 15.200mm 0.5984" (1 hole Total plated holes unplated through holes: merged pull request 'More schematics' (#3) from schematic by Eeschema 5.1.10-88a1d61d58~90~ubuntu20.04.1 Component Count: 76 Refs C2, C5, C6, C8, C9 D1, D2, D3, D4, D5, D8, D9, D10 100V 0.15A standard switching diode, DO-35 | | J3, J4, J5 | 3 | A1M | \*\*Potentiometer, 9 mm or 16 mm have been tested and there could be other values, ceramic may work, test debouncing. Maybe enlarge footprint if needed. Subject: [PATCH 03/18] tweaks layout with input from sam format.
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Normal 3.422964e-001 -5.872896e-001 7.334331e-001. - 43915-xx12, With thermal vias in pads, 4.
- 5/12-V-7.5-ZB Terminal Block, 1732441 (https://www.phoenixcontact.com/online/portal/gb/?uri=pxc-oc-itemdetail:pid=1732441), generated with kicad-footprint-generator.