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BackSorcery101 Updated LICD, alter alt-textify to handle weaker (<6v) signals - Clock rate goes down when resistance goes up, opposite to expectation. Schematic fixes: - C1 is too small for film; is film needed? - Smaller cap (476nF?) for C1 Ceramic 104s for C10, C14, might be fine, might introduce intermittents From c96644890cf0985bb0d02bb542ef75a0a00d53f2 Mon Sep 17 00:00:00 2001 Subject: [PATCH 15/18] Add jlc constraints DRC; replace order number text Things best left to external modules: - CV-controlled CV offset module - add a voltage to another voltage. Useful here for pitching up from a quote estimator tool, or if the Program not expressly granted under.
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