Pin="TN"/> main MK_VCO/Fireball/Fireball_panel.kicad_pro 505 lines { "board": { More tweaks after pro review "extra_units": "error", "global_label_dangling": "warning", "hier_label_mismatch": "error", "label_dangling": "error", "lib_symbol_issues": "warning", More tweaks after pro review Apply jlcpcb's design rules, small fixes for those 972e45fb78 Go to file From 33729ec97f6dd2ed68c4ca06088ce0b21651948d Mon Sep 17 00:00:00 2001 Subject: [PATCH] New KiCad version; non Al panel Gerbers # Netlist files (exported from Eeschema *.csv *.lck ########################## # Additional ignored # KiCad backups folders *-backups # Compressed files *.zip # Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains T1 3.200mm 0.1260" (4 holes) (with 4 slots T2 5.000mm 0.1969" (1 hole) T3 7.000mm 0.2756" (6 holes) T4 10.000mm 0.3937" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole Total plated holes count 0 Hardware/Panel/precadsr-panel-Gerbers/precadsr-panel-CmtUser.gbr Normal file Unescape Hardware/PCB/precadsr/ao_symbols.dcm Normal file Unescape Docs for installation and contributing. D40f7ca1ca Experimenting with more representative footprints. Consider moving C11 so it does not arrive in a Work; main MK_VCO/Fireball/Fireball_panel.kicad_prl 78 lines { "board": { updates to rev 2 beta by adding +5V, and both trigger/gate and CV routing updates led holes to 5mm + unplated, and revises jack footprint power word stun initial commit by { "board": { More tweaks after pro review Fireball/Fireball.kicad_pro | 4 .../PCB/precadsr_aux_Gerbers/precadsr-PTH.drl | 99 .../precadsr_aux_Gerbers/precadsr-job.gbrjob | 2 .../OttosIrresistableDance.kicad_sch | 5 | 2N3904 | 0.2A Ic, 40V Vce, Small Signal NPN Transistor, TO-92.