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BackTemp_* # Compressed files *.zip # Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains T1 3.200mm 0.1260" (4 holes) (with 4 slots T2 5.000mm 0.1969" (1 hole Total plated holes count 16 Not plated through holes are merged with plated holes Total unplated holes count 0 Hardware/Panel/precadsr-panel-Gerbers/precadsr-panel-CmtUser.gbr Normal file Unescape Hardware/PCB/precadsr_aux_Gerbers/precadsr-B_Cu.gbr Normal file Unescape Hardware/PCB/precadsr/ao_tht.pretty/Potentiometer_Alpha_RD901F-40-00D_Single_Vertical_CircularHoles_centered.kicad_mod Normal file View File Panels/futura medium condensed bt.ttf Normal file Unescape Hardware/PCB/precadsr/ao_tht.pretty/Potentiometer_Alpha_16mm_Single_Vertical.kicad_mod Normal.
- TMLM 05 ACDC-Converter, TRACO TMLM Series.
- Capacitor, http://www.wima.de/DE/WIMA_MKS_02.pdf C Rect series Radial pin.
- -0.748097 0.586806 facet normal -0.430896 -0.353629 0.830226.
- 160x104 RS-232 I2C or SPI.
- Build images Images/PXL_20210831_000922493.jpg | Bin 0.