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1 5.39134 21.8333 vertex -1 3.18579 20.5 vertex 0.95 7.77656 6.96334 vertex -0.95 0 22.5 vertex 0.95 6.11494 21.5472 vertex -0.95 6.11494 21.5472 vertex -0.95 0 22.5 vertex -0.95 0 20.5 facet normal 2.360004e-15 -8.103531e-16 -1.000000e+00 facet normal 9.996590e-01 -2.611259e-02 1.272368e-07 vertex -1.045770e+02 9.890126e+01 3.455000e+01 vertex -9.657885e+01 9.175388e+01 1.855000e+01 vertex -1.045657e+02 9.849792e+01 3.455000e+01 vertex -1.045318e+02 9.809589e+01 3.455000e+01 facet normal 8.468809e-001 -5.317827e-001 0.000000e+000 vertex -4.091196e+000 3.859275e+000 9.983999e+000 vertex -4.873291e+000 -2.885563e+000 1.747200e+001 facet normal -9.345903e-01 -2.605745e-03 -3.557165e-01 facet normal -2.880153e-004 -5.040268e-004 -9.999998e-001 ## Documentation: * [Schematic](Docs/precadsr.pdf) * PCB layout: [front](Docs/precadsr_layout_front.pdf), [back](Docs/precadsr_layout_back.pdf) * [BOM](Docs/precadsr_bom.md) * [Build notes](Docs/build.md ## GitHub repository ## Git repository From 40ce306867b3d353457e134a232ee65f5767bece Mon Sep 17 00:00:00 2001 Subject: [PATCH] Update 'README.md' Update 'README.md' From ec67859b1c2779470b99801ce69f8850b83fa3e1 Mon Sep 17 00:00:00 2001 From 1a5b794ab9bac64e7d0bb61780efe97d27a2e668 Mon Sep 17 00:00:00 2001 Subject: [PATCH] Change transistor footprint to inline_wide, fix DRC ground plane 5e32fb4fc0953f2a10f8dc9cf7a0a3653bcbf4f2 @circuitlocution.com created pull request 'Fix rail clearance issues, make all power traces large "rules": { PCB initial layout, no traces "silk_line_width": 0.15, PCB initial layout, no traces "silk_line_width": 0.15, "silk_text_italic": false, "silk_text_size_h": 1.0, "silk_text_size_v": 1.0, PCB initial layout, no traces "min_copper_edge_clearance": 0.0, PCB initial layout, no traces Using the Precision ADSR build notes | C7, C12, C13 | 3 | 10uF | Electrolytic capacitor | | | | | | | U2 | 1 | 10R | Resistor | .

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