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0.925211 0.0989244 facet normal 8.050200e-02 7.673375e-03 -9.967249e-01 vertex -1.074583e+02 9.725134e+01 1.288679e+01 facet normal 0.0980427 -0.995182 -7.23691e-06 facet normal 0.956924 -0.29034 -9.5392e-07 facet normal 4.330093e-01 0.000000e+00 -9.013895e-01 facet normal 9.593087e-01 -2.495751e-03 -2.823485e-01 facet normal -0.0127267 0.705404 0.708692 facet normal -0.538413 0.714663 0.446506 facet normal -0.075425 0.766035 -0.638358 facet normal 3.734794e-001 -6.399524e-001 6.715460e-001 facet normal -4.589969e-01 8.884379e-01 0.000000e+00 vertex -8.524144e+01 9.815134e+01 1.755000e+01 facet normal -0.0620422 -0.0777927 0.995037 vertex -1.77842 7.79176 19.9496 facet normal -0.820339 -0.163177 -0.548103 vertex 3.36082 0 18.4724 facet normal -0.773006 0.634399 4.46254e-06 facet normal 0.124337 0.0369052 0.991554 facet normal 2.280652e-15 -5.560293e-15 1.000000e+00 facet normal 0.243779 -0.297045 0.92322 facet normal 0 0.833884 0.55194 Latest commits for file Schematics/SynthMages.pretty/Perfboard_1x12.kicad_mod # Temporary files *.lck # Netlist files (exported from Eeschema *.csv *.lck ########################## # Additional ignored # KiCad backups folders temp_* # Compressed files *.zip # Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains T1 3.200mm 0.1260" (4 holes) T5 15.200mm 0.5984" (1 hole Total plated holes count 16 Not plated through holes: unplated through holes: ============================================================= ec67859b1c2779470b99801ce69f8850b83fa3e1 Start of LM13700 version to see why main.

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