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BackV3.2 3afa35e4b1 PCB initial layout, no traces "min_copper_edge_clearance": 0.0, PCB initial layout, no traces "min_copper_edge_clearance": 0.0, PCB initial layout, no traces Fireball/Fireball.kicad_prl | 8 "active_layer_preset": "All Copper Layers", re-re-remove the mysterious extra trace 5040873587dbb57684343269abab88d35cf7124b Update Schematics/schematic_bugs_v1.md Schematics/schematic_bugs_v1.md | 1 | Synth_power_2x5 | 2x5 pin shrouded header 2.54 mm 2x5 | | | | J5, J12, J13 | 3 | 2_pin_Molex_header | 2 pin Molex header 2.54 mm spacing"/>