synth_tools

Back

Version From a295bd71525185b616796bece6c52d455905c9b6 Mon Sep 17 00:00:00 2001 Subject: [PATCH] Finished PCB, passes all passable DRCs .../Unseen Servant/Unseen Servant.kicad_pro Normal file View File Hardware/Panel/precadsr-panel-Gerbers/precadsr-panel.drl Normal file Unescape Schematics/Unseen Servant/Unseen Servant.kicad_prl | 75 .../precadsr-panel-MaskTop.gts | 75 .../Push_button_A-5050.kicad_mod | 13 commits to main since this release Submitted to fab on 2024/01/24. From b11a8d31874f2e074879a668b4f6eb5f32915bd6 Mon Sep 17 00:00:00 2001 Subject: [PATCH] Add note resulting from real TL0x4s 5cacbfea2e Add polygon calculation for wing plates 5cacbfea2e523d618ea3bcbc0bca9c37eb36f10d Update README.md 32ece2d681b26731bad50902587b988d6a79e43e updated README.md README.md | 12 delete mode 100644 Schematics/SynthMages.pretty/Potentiometer_Alpha_RD901F-40-00D_Single_Vertical_CircularHoles_Shaft_Centered.kicad_mod create mode 100644 Panels/luther_triangle_vco_quentin_v3_only_art.stl create mode 100755 Panels/FireballSpell.dxf create mode 100644 Schematics/SynthMages.pretty/SLIDE_POT_0547.kicad_mod create mode 100644 Hardware/PCB/precadsr/potsetc.kicad_sch delete mode 100644 Hardware/PCB/precadsr_aux_Gerbers/precadsr-Edge_Cuts.gbr create mode 100644 Images/IMG_6771.JPG create mode 100644 3D Printing/Panels/AD&D 1e spell names in Filmoscope Quentin/Panels/MAGIC MISSILE VCF.png' Delete '3D Printing/AD&D 1e spell names in Filmoscope Quentin/Panels' Delete '3D Printing/Panels/SPIDER CLIMB.png' 3D Printing/Panels/AD&D 1e spell names in Filmoscope Quentin typeface Created by Cvpcb (2015-03-25 BZR 5536)-product date = sam. 04 avril 2015 11:21:18 UTC update=Tue 20 Apr 2021 12:09:41 PM EDT Thu 22 Apr 2021 10:22:18 AM EDT Sat 28 Aug 2021 07:18:14 PM EDT Generated from schematic into main Merge pull request 'Fix rail clearance issues, make all power traces large "rules": { PCB initial layout, no traces "solder_mask_clearance": 0.0, PCB initial layout, no traces "silk_line_width": 0.15, "silk_text_italic": false, "silk_text_size_h": 1.0, "silk_text_size_v": 1.0, "silk_text_thickness": 0.15, "silk_text_upright": false, "zones": { "min_clearance": 0.5 } }, updates to rev 2 beta f12031bb41 updates to rev 2 beta by adding +5V, and both trigger/gate and CV routing } ], "meta": { More tweaks after pro review "design_settings": { "defaults": { PCB initial layout, no traces Using the Precision ADSR with retriggering and looping modifications * Bourns PTL series, such as: * https://www.mouser.com/ProductDetail/Bourns/PTL30-15O0-105A2?qs=fV9UsjselOEqdQiKFAm%2Fog%3D%3D (A1M, orange LED, 30mm travel, 15mm shaft https://www.digikey.com/en/products/detail/bourns-inc/PTL30-15R0-103B1/3781301 (red B10K) and https://www.digikey.com/en/products/detail/bourns-inc/PTL30-15O0-105A2/7314942 (orange A1M * The SPDT toggle switches 74231bd333 Port in fixes from v1.1 74231bd333b049ab7b99365de62d937af76b0e42 Finish PCBs Checkpoint after tweaking footprints some more, starting over at 14hp cd18ed43dc Added hard sync (to a clock/gate/trigger input) Quantizer Interfaces to digital components and interconnects between middle and bottom boards. Final work on PCB with on-board components hard_sync traces added but maybe won't keep From 52a9fa26f6a6a8c4f7e3fc085f8b6ccdd7541277 Mon Sep 17 00:00:00 2001 Subject: [PATCH] Update current state of project. Add cascading input and output jacks 972d8b1e0797912e848110b19e1af10ed411bbbb tweaks layout with input from sam format (units 3) (units_format 1) (precision 4 style (thickness 0.1) (arrow_length 1.27) (text_position_mode 0) (extension_height 0.58642) (extension_offset 0) keep_text_aligned Add control label font so we.

New Pull Request

Labels Milestones