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Back# Additional ignored # KiCad backups folders *-backups # Compressed files *.zip # Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes are merged with plated holes count 0 Hardware/Panel/precadsr-panel-Gerbers/precadsr-panel-CmtUser.gbr Normal file View File 3D Printing/Cases/Eurorack 2-Row/d0689b08d90f6b787384d8519c91dddf_preview_featured.jpg Executable file Unescape Hardware/PCB/precadsr/ao_tht.pretty/Potentiometer_Alpha_16mm_Long_Pin_Single_Vertical.kicad_mod Normal.
- Normal -0.778618 0.416179 0.469626.
- Normal -9.493289e-01 3.142843e-01 2.193642e-04 vertex -1.042727e+02.
- -4.87063 4.68184 7.03353 facet normal 0.0572764.
- Normal -9.198330e-01 -3.923101e-01 2.985835e-04 vertex -1.039194e+02 9.589675e+01.