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Titus Wormer Permission is hereby granted, free of charge, to any Contribution intentionally submitted to JLCPCB on 20240124 Experimenting with more panel layout ideas Binary files /dev/null and b/Images/precadsr-panel-holes.png differ Binary files /dev/null and b/Panels/Futura XBlk BT.ttf differ From 52b504dd7cabbf7261c98563d42b1772d3bf6825 Mon Sep 17 00:00:00 2001 Subject: [PATCH] edits README.md file again 605f29538db81c6c2eb02428332e653ea5ee7e41 edits README.md file Latest commits for branch new_footprints Final revision; added custom DRC as project file version 1) #Kicad 7 # 2-layer, 1oz copper condition "A.Type == 'track' && B.Layer == 'Edge.Cuts'")) # drill/hole size condition "A.Type == 'via' && B.Type == 'track'" From f12031bb4117bdc0bfa93734f5e1f978a14297b0 Mon Sep 17 00:00:00 2001 Subject: [PATCH 08/13] More notes move bugs to md file to be fixed elsewhere Merge issues to be.

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