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0.0735183 vertex 4.24331 2.97557 21.7998 vertex 4.03376 2.95564 21.7809 facet normal -0.586516 -0.714669 0.381113 facet normal 4.866822e-001 -8.343557e-001 2.588264e-001 vertex -3.405740e+000 3.795491e+000 2.475471e+001 facet normal -0.290168 0.956976 0 facet normal -8.191610e-001 -3.647190e-003 5.735521e-001 facet normal 3.779560e-001 -6.476000e-001 6.616370e-001 facet normal 0.796854 0.241723 0.553709 facet normal 4.328583e-001 7.575029e-001 4.886952e-001 facet normal -0.0976054 -0.989316 0.108289 facet normal 8.477229e-01 3.604418e-03 5.304271e-01 facet normal 0.260571 0.962888 0.0703571 facet normal -0.773006 0.634399 4.46254e-06 facet normal 0.097471 0.989338 0.108209 facet normal -0.77255 -0.634852 0.0113593 vertex 3.28327 -4.80177 21.335 vertex -6.91995 -1.06598 10.3435 facet normal 0.195101 -0.980783 -5.85608e-06 vertex 0.4 3.34543 7.96516 vertex -1.31069 -3.16429 6.59 vertex 0 -9.96384 2.94279 facet normal 0.758285 0.622326 0.194199 facet normal -0.980785 0.195093 -6.4466e-07 vertex 3.21351 -1.06324 6.59 facet normal 0.111507 0.258352 0.959594 facet normal -0.459965 -0.538537 0.705981 facet normal -9.468859e-01 -3.215698e-01 0.000000e+00 vertex -9.578389e+01 1.059137e+02 3.455000e+01 facet normal 1.304260e-001 -2.235993e-001 9.659153e-001 vertex -5.201906e+000 -1.091369e+000 2.494118e+001 facet normal -0.124621 0.886065 0.446496 vertex -5.20841 4.17623 7.5439 facet normal 0.491592 -0.262761 0.830237 facet normal 0.768445 0.630708 0.108161 facet normal 0.331801 -0.353615 0.874566 facet normal 7.990003e-01 6.013306e-01 3.314663e-04 vertex -9.176090e+01 1.033860e+02 3.455000e+01 facet normal 0.0220277 -0.097037 0.995037 vertex -2.47057 -7.61424 19.9477 vertex -2.09439 -9.17613 20.0916 vertex 4.9862 6.2525 19.9501 facet normal -0.325732 0.734388 0.595461 facet normal 0.247224 0.963862 0.099246 facet normal 0.95694 0.290287 0 vertex 2.42705 1.76336 0 vertex 10.1904 0 0 VCO details from Moritz Klein (and derivatives Fix rail clearance issues, make all power traces large "rules": { PCB initial layout, no traces "silk_line_width": 0.15, PCB initial layout.

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