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2.6 (mid 4.633903 -1.509328 (end 4.864184 -1.122795 (mid 1.143021 2.192818 (end 0.1836 1.098807 (mid 0.446097 -1.509328 (end 6.09 -2.01 (end -1.01 2.73 (end 0.8 -1.75 (mid 4.831221 0.949055 (end 2.54 2.48 (mid 0.248779 0.949055 (end 2.54 2.6 (mid 4.633903 -1.509328 (end 4.864184 -1.122795 (mid 1.143021 2.192818 (end 0.1836 1.098807 (mid 0.446097 -1.509328 (end 6.09 -2.01 (end -1.01 2.73 (end 0.8 -1.75 (mid 4.831221 0.949055 (end 0.786375 -1.753625 (end -3.29 -15.37 (end 5.83 5.21 (end -1.98 3.91 (end 5.83 5.21 (end 6.22 -15.76 (end -3.68 5.6 (end 6.22 5.6 (end 6.22 -15.76 (end -3.18 -15.26 (end -3.18 -3.03 (end -1.98 3.91 (end 5.83 5.21 (end 6.22 5.6 (end -3.68 5.6 (end 6.22 -15.76 (end -3.18 4.1 (end -2.18 5.1 (end -3.18 4.1 (end -2.18 5.1 (end -1.33 0 (end -0.883605 1.0875 (end -0.633605 1.3375 (end 3.75 0 (end -0.261252 0.735 (end 0.261252 -0.735 (end -0.261252 0.735 (end 0 -0.127 (end 0 -4.45 (end -4.5 -4.5 (end 4.5 -4.4 (hatch full 0.508 (end -3.29 -15.37 (end -3.29 5.21 (end -1.98 -3.03 (end 5.72 5.1 (end -1.33 1.33 (end -1.33 -1.27 (end 1.33 2.579 (end 1.29 2.58 (end -1.554775 1.475 (end -1.304775 1.725 (end 3.87 0 (end 1.8 1.8 (end -0.635 1.27 (end 1.27 -6.35 (end 1.27 -13.97 (end 2.286 1.016 (end -2.286 -1.016 (offset 0.254) hide (end -3.81 -2.54 (end -2.54 -5.08 (offset 1.016) hide (end 1.016 2.54 (end -1.016 -2.54 (offset 0) hide From 5a4d5850276107dae545a96ba13aec19af1bdbba Mon Sep 17 00:00:00 2001 Subject: [PATCH] Align panel to integer pseudo-origin, remove testing text, decrease title label font size to 9mm and align it precisely for repeatability b11a8d31874f2e074879a668b4f6eb5f32915bd6 Change transistor footprint to inline_wide, fix DRC ground plane 5e32fb4fc0953f2a10f8dc9cf7a0a3653bcbf4f2 @circuitlocution.com created pull request 'new_footprints' (#5) from new_footprints into main Reviewed-on: https://gitea.circuitlocution.com/synth_mages/MK_VCO/pulls/3 Merge pull request synth_mages/MK_VCO#5 613d1b6f7e Merge pull request 'Fix rail clearance issues, add PCB slot, more options for potentiometer spoke placement' (#1) from bugfix/10hp into main afea9d5a2cf23e2a33a2927086270d4d602f5a2b Final revision; added custom DRC as project file afea9d5a2cf23e2a33a2927086270d4d602f5a2b Final revision; added custom DRC as project file tstamp e90beec6-952b-474b-a043-0f4708c5b9c2) Final revision; added custom DRC as project file version 1) #Kicad 7 # 2-layer, 1oz copper condition "A.Type == 'pad' && A.Fabrication_Property == 'Castellated pad'")) # clearance If desired, copy the files from the IDC through the power subsystem footprint "Perfboard_2x12" (version 20221018) (generator.

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