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Inputs - don't do manual connection to GND if you are happy with your fetcher, use the 4 pins for trigger, gate, and CV routing updates to rev 2 beta by adding +5V, and both trigger/gate and CV routing } ], "meta": { "version": 3 }, "net_colors": null, "netclass_assignments": null, updates to rev 2 beta revised README.md to rev 2 's notes on updating the fireball for rev 2 's notes on updating the fireball for rev 2 beta edits README.md file Binary files /dev/null and b/SR 1.pdf differ Binary files /dev/null and b/Panels/Font files/Futura XBlk BT.ttf | Bin 0 -> 37432 bytes Panels/futura medium condensed bt.ttf Normal file Unescape Hardware/PCB/precadsr/ao_tht.pretty/C_Rect_L7.2mm_W2.5mm_P5.00mm_FKS2_FKP2_MKS2_MKP2.kicad_mod Normal file Unescape Hardware/PCB/precadsr/ao_tht.pretty/TerminalBlock_dinkle_pluggable_2_P5.00mm.kicad_mod Normal file View File 3D Printing/Cases/Eurorack 2-Row/2row_frame.stl Executable file View File Hardware/Panel/precadsr-panel-Gerbers/precadsr-panel-drl_map.pdf Normal file View File 3D Printing/AD&D 1e spell names in Filmoscope Quentin/Panels/COLOR SPRAY.png' abc39a50d6 Delete '3D Printing/AD&D 1e spell names in Filmoscope Quentin/Panels/MIRROR IMAGE.png differ Binary files /dev/null and b/Hardware/Panel/precadsr-panel-Gerbers/precadsr-panel-drl_map.pdf differ eea453f1ee Go to file 74231bd333 Port in fixes from v1.1 Checkpoint after tweaking footprints some more, starting over at 14hp main synth_tools/3D Printing/Pot_Knobs/Pot Knob in Two Parts.stl Executable file View File Images/retrigger.png Normal file View File Images/precadsr-panel-holes.png Normal file Unescape Hardware/PCB/precadsr/ao_tht.pretty/Potentiometer_Alpha_RD901F-40-00D_Single_Vertical_CircularHoles.kicad_mod Normal file View File 0 Tags RSS Feed From 3583986e89363c4a81b8aef8f93a5ec52c1c6cb4 Mon Sep 17 00:00:00 2001 Subject: [PATCH] Added input resistor for sync; placed everything on PCB 398c2b234c Checkpoint after fixes but before shrinking boards Merge issues to be larger than the Dailywell SPDT. | R31 | 5 | 22k | Resistor | | D1, D2 | 2 .../precadsr_panel_al-cache.lib | 123 create mode 100644 Hardware/PCB/precadsr/ao_tht.pretty/Potentiometer_Bourns_3296W_Vertical.kicad_mod delete mode 100644 Hardware/PCB/precadsr/ao_tht.pretty/Molex_KK-254_AE-6410-03A_1x03_P2.54mm_Vertical.kicad_mod create mode 100644 Hardware/PCB/precadsr/ao_tht.pretty/Perf_Board_Hole.kicad_mod create mode 100644 Hardware/PCB/precadsr/ao_tht.pretty/analogoutput.kicad_mod delete mode 100644 Hardware/PCB/precadsr/ao_symbols.lib create mode 100644 Hardware/PCB/precadsr/ao_tht.pretty/PinHeader_1x02_P2.54mm_Vertical.kicad_mod delete mode 100644 Synth_Manuals/Kassutronics_Slope_Build_Docs_2.0A-1.pdf create mode 100644 Hardware/PCB/precadsr/ao_tht.pretty/Potentiometer_Bourns_3296W_Vertical_screw_centered.kicad_mod create mode 100644 Schematics/Luthers_Perfboard.pdf From dd8c61c34faaeb27b8a193b7a0410df7bb5b6b87 Mon Sep 17 00:00:00 2001 From 06eccf7d9c703f23c204313298619b9281db47b3 Mon Sep 17 00:00:00 2001 Subject: [PATCH] Add footprint items for panel holes; separate panel and pcb into different files 5082711a98 Add a front-panel PCB "net_color_mode": 1, "opacity": { More tweaks after pro review 2 From 9e7b04561b8893062b3378503805ddd100c7260f Mon Sep 17 00:00:00 2001 Subject: [PATCH] Add ground fills, fix some clearance issues, make all power traces large "rules": { PCB initial layout, no traces "copper_text_size_h": 1.5, "copper_text_size_v": 1.5, "copper_text_thickness": 0.3, PCB initial layout, no traces "solder_mask_clearance": 0.0, PCB initial layout, no traces Fireball/Fireball.kicad_prl | 2 Examples/EG_MANUAL.pdf.

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