3
1
Back

Vertex -4.016004e+000 -5.120441e-002 2.475471e+001 facet normal -0.682464 0.560089 0.46962 facet normal 0.695475 0.464692 -0.548065 facet normal 0.703595 0.707109 0.0703597 vertex 10.8957 3.36088 0.18985 facet normal 2.588537e-001 1.152626e-003 9.659159e-001 vertex 2.654655e+000 -4.556911e+000 2.494118e+001 vertex 3.505631e+000 3.987758e+000 2.494118e+001 facet normal -0.422016 0.362608 0.830914 vertex 5.64771 4.69512 7.09873 facet normal -4.496525e-001 -7.868906e-001 4.226297e-001 facet normal -0.952376 -0.288901 0.0975479 facet normal -3.534176e-01 -8.635605e-03 -9.354258e-01 vertex -1.055858e+02 9.725134e+01 1.277435e+01 facet normal -0.18908 0.787327 0.586827 facet normal 9.534050e-01 -7.361366e-03 3.016037e-01 facet normal -0.174189 -0.420502 0.890414 facet normal 0.6852 0.343403 0.64232 facet normal -4.720726e-001 8.093091e-001 3.495229e-001 vertex 1.348450e+000 -3.946332e+000 2.480400e+001 facet normal 2.777228e-15 -1.366784e-15 -1.000000e+00 facet normal 2.793007e-02 9.996099e-01 -0.000000e+00 facet normal 0.767777 -0.634425 0.0895734 facet normal 6.933023e-15 -1.000000e+00 -6.787200e-14 facet normal -9.09242e-05 0.114971 0.993369 vertex 6.2584 0 7.81508 vertex -6.25374 0 7.81454 facet normal -9.527802e-01 3.036606e-01 -2.293352e-04 facet normal 0.309854 -0.74806 0.586853 vertex 3.63499 -2.35444 19.9 facet normal 0.69044 -0.423077 0.58677 facet normal -1.425907e-01 -2.870850e-03 9.897776e-01 facet normal 0.403621 -0.491817 0.771496 vertex -7.11876 4.7566 5.56266 facet normal 0.0623605 -0.633165 0.771501 vertex 0 7.49999 6.0001 vertex 4.16678 -6.23601 6.0001 vertex -2.87011 6.92909 6.0001 vertex 5.30329 -5.30329 6.0001 vertex -6.92909 -2.87012 6.0001 vertex 6.92909 -2.87011 6.0001 vertex 0 -7.79364 5.97318 facet normal -2.304122e-004 -4.032215e-004 -9.999999e-001 Latest commits for file Envelope/Envelope.kicad_pro Latest commits for file Images/befaco_vcadsr.png Add befaco image for inspo Add befaco image for inspo Add befaco image for inspo Looping mode, allowing attack-decay envelopes to repeat as long as a gate is present, or, if nothing is plugged into CLOCK. A notable issue with this design is ancient; maybe an updated one exists with current ICs?

New Pull Request