Labels Milestones
BackLTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: T5 15.200mm 0.5984" (1 hole) T3 7.000mm 0.2756" (6 holes) T4 10.000mm 0.3937" (4 holes) (with 4 slots T2 5.000mm 0.1969" (1 hole) Total plated holes count 0 Hardware/Panel/precadsr-panel-Gerbers/precadsr-panel-CmtUser.gbr Normal file Unescape Hardware/PCB/precadsr_Gerbers/precadsr-B_Paste.gbr Normal file View File Thu 22 Apr 2021 10:45:56 AM EDT R14, R15 values changed\ndue to availability Kassu used 1 uF | Polarized capacitor | | | | | | | | R4, R6, R7 | 3 | 10uF | Polarized capacitor | | | | C1 | 1 | LM358 | Low-Power, Dual Operational Amplifiers, DIP-8/SOIC-8/TO-99-8"/>