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BackSalient bits of blogs into Tiny Tiny RSS entries. # For PCBs designed using KiCad: http://www.kicad-pcb.org/ # Format documentation: https://kicad.org/help/file-formats/ # Temporary files fp-info-cache # Netlist files (exported from Eeschema) *.net # Autorouter files (exported from Eeschema *.csv *.lck ########################## # Additional ignored # KiCad backups folders temp_* # Compressed files *.zip # Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: T5 15.200mm 0.5984" (1 hole) T3 7.000mm 0.2756" (6 holes) T4 10.000mm 0.3937" (4 holes T5 15.200mm 0.5984" (1 hole T3 7.000mm 0.2756" (6 holes) T4 10.000mm 0.3937" (4 holes T5 15.200mm 0.5984" (1 hole Total plated holes count 16 ============================================================= Total unplated holes count 16 ============================================================= Total unplated holes count 0 Minor layout tweaks Schematics/Fireball_VCO.pdf | Bin 0 -> 36336 bytes create mode 100755 MK_VCO_RADIO_SHAEK_W_PARTS.diy create mode 100644 Hardware/PCB/precadsr_Gerbers/precadsr-Edge_Cuts.gbr create mode 100644 Schematics/Enlarge/Enlarge.kicad_prl.
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