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Hardware/PCB/precadsr/ao_tht.pretty/Arduino_Nano.kicad_mod Normal file Unescape Hardware/PCB/precadsr/precadsr.pro Normal file Unescape Hardware/PCB/precadsr/ao_tht.pretty/PinHeader_1x03_P2.54mm_Vertical.kicad_mod Normal file View File Latest commits for file Schematics/SynthMages.pretty/Perfboard_1x12.kicad_mod # Temporary files *.000 *.bak *.bck *.kicad_pcb-bak *.kicad_sch-bak *-backups */fp-info-cache *.kicad_prl *.sch-bak *~ _autosave-* *.tmp *-save.pro *-save.kicad_pcb fp-info-cache # Autorouter files (exported from Eeschema *.csv *.lck ########################## # Additional ignored # KiCad backups folders *-backups # Compressed files *.zip # Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes are merged with plated holes count 16 Not plated through holes: unplated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) T5 15.200mm 0.5984" (1 hole T3 7.000mm 0.2756" (6 holes) T4 10.000mm 0.3937" (4 holes T5 15.200mm 0.5984" (1 hole Total plated holes count 0 Hardware/Panel/precadsr-panel-Gerbers/precadsr-panel-CmtUser.gbr Normal file Unescape module label(string, size=4, halign="center", font=default_label_font) { Latest commits for file Panels/Futura Heavy BT.ttf rename to 3D Printing/Cases/6u_wing_v1.scad Binary files /dev/null and b/3D Printing/AD&D 1e spell names in Filmoscope Quentin/MIRROR IMAGE.png create mode 100644 Hardware/PCB/precadsr/Kosmo_panel.pretty/fastestenv_Pot_Hole.kicad_mod create mode 100644 Fireball/Fireball.kicad_dru create mode 100644 Schematics/SynthMages.pretty/Jack_3.5mm_QingPu_WQP-PJ398SM_Vertical_CircularHoles_Socket_Centered.kicad_mod.

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