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BackFile fp-info-cache Normal file View File # For PCBs designed using KiCad: http://www.kicad-pcb.org/ # Format documentation: http://kicad-pcb.org/help/file-formats/ # Temporary files *.000 *.bak *.bck *.kicad_pcb-bak *.kicad_sch-bak *-backups *.kicad_prl *.sch-bak *~ _autosave-* *.tmp *-save.pro *-save.kicad_pcb fp-info-cache *.lck # KiCad backups folders *-backups # Compressed files *.zip # Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains T1 3.200mm 0.1260" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole) T3 7.000mm 0.2756" (6 holes T4 10.000mm 0.3937" (4 holes) (with 4 slots T2 5.000mm 0.1969" (1 hole) Total plated holes unplated through holes: unplated through holes: ============================================================= From a22bca6d29ddc0a54597dab4d11ad9ab7e48e3c6 Mon Sep 17 00:00:00 2001 Subject: [PATCH] Delete 'Panels/futura light bt.ttf' Panels/futura medium condensed bt.ttf' Delete 'Panels/futura light bt.ttf' Panels/futura medium bt.ttf | Bin 0 -> 30552 bytes From cb59d1e9c06865f5bebe8c7ee0afa4859e0766b2 Mon Sep 17 00:00:00 2001 Subject: [PATCH] Apply jlcpcb's design rules, small fixes for those colors that are managed by, or is derived from this software for any code that a.
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