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Back*.dsn *.kicad_pcb-bak *.kicad_sch-bak *-backups *.kicad_prl *.sch-bak *~ _autosave-* *.tmp *-save.pro *-save.kicad_pcb fp-info-cache *.lck # KiCad backups folders temp_* # Compressed files *.zip # Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes are merged with plated holes count 16 ============================================================= Total unplated holes count 16 Not plated through holes are merged with plated holes unplated through holes: merged pull request 'More schematics' (#3) from schematic into main created pull request 'Finish schematic, add PDF Schematics/Fireball_VCO.pdf | Bin 0 -> 106084 bytes Panels/luther_triangle_10hp.stl | Bin 0 -> 676484 bytes 3D Printing/Panels/image.png | Bin 0 -> 121262 bytes Panels/FireballSpell_Large_bw.png | Bin 0 -> 7868 bytes Panels/a_color_icon_of_a_flying_fireball.webp | Bin 0 -> 16700 bytes .../Panels/SPIDER CLIMB.png | Bin 0 -> 11310848 bytes Synth_Manuals/Module Summaries.ods
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