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BackPlug Shenzhen Jing Tuo Jin Electronics Co 918-118A2021Y40002 ( https://datasheet.lcsc.com/lcsc/1912111437_Jing-Extension-of-the-Electronic-Co--918-118A2021Y40002_C399939.pdf ) also compatible with SOIC-8, 3.9x4.9mm² body, exposed pad, thermal vias, http://www.ti.com/lit/ds/symlink/drv8870.pdf 20-Pin Thermally Enhanced Thin Shrink Small Outline http://www.vishay.com/docs/49633/sg2098.pdf SOP, 16 Pin (http://www.ti.com/lit/ds/symlink/drv8801.pdf#page=31 MO-220 variation VJJD-2), generated with kicad-footprint-generator ipc_gullwing_generator.py TSSOP, 16 Pin (https://www.haloelectronics.com/pdf/discrete-ultra-100baset.pdf), generated with kicad-footprint-generator Molex 734 Male header (for PCBs); Angled solder pin 1 (so is open or ground). Part of speed \nswitch mod (0 F.Cu signal (31 B.Cu signal (32 "B.Adhes" user "B.Adhesive" (33 "F.Adhes" user "F.Adhesive" (34 "B.Paste" user (35 F.Paste user hide (48 B.Fab user hide (0 "F.Cu" signal (31 B.Cu signal (32 B.Adhes user (33 F.Adhes user hide 42 Eco1.User user hide (35 F.Paste user hide 42 Eco1.User user hide From d48d677c9103ec90137a6830434841a576342e9a Mon Sep 17 00:00:00 2001 Subject: [PATCH] schematics tweaks README.md Normal file Unescape Hardware/PCB/precadsr/ao_tht.pretty/DIP-14_W7.62mm_Socket_LongPads.kicad_mod Normal file View File fp-info-cache Normal file Unescape