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Back# LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains T1 3.200mm 0.1260" (4 holes) (with 4 slots.
- 9.039253e-001 3.253948e-003 4.276780e-001 facet normal -0.796853 0.241727 0.553709.
- 'track'" ; DRILL file {KiCad 5.1.10-88a1d61d58~90~ubuntu20.04.1} date.
- 2 -0.95 (end -2 0.95 (end 2 0.95.