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BackPage "Panel Style Guide" cannot be undone. Continue? Fdd5744d78 Checkpoint after tweaking footprints some more, starting over at 14hp cd18ed43dc Added hard sync to schematic, laid out PCB with exploratory 8hp layout 77735c00cc3285131373f5cfc61b82eab5963d12 Update README.md 5505000471ab249f70d985a8f814bce077fb47b2 Update README.md Update README.md 5505000471ab249f70d985a8f814bce077fb47b2 Update README.md Don't put R8 so close to R26 D36/R47 too close - Clock rate goes down when resistance goes up, opposite to expectation. C1 is too small for a single 0.15 mm² wires, basic insulation, conductor diameter 1.25mm, outer diameter 3.5mm, size 38.5x7.6mm^2, drill diamater 1.3mm, pad diameter 2.6mm, see http://www.farnell.com/datasheets/100425.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_RND THT terminal block RND 205-00246 pitch 10.2mm size 25.4x8.3mm^2 drill 1.3mm pad 2.5mm terminal block RND 205-00051, 8 pins, https://www.diodes.com/assets/Datasheets/ZXSBMR16PT8.pdf 8-pin SOT-383FL package, http://www.onsemi.com/pub_link/Collateral/ENA2267-D.PDF SOT-543 4 lead surface package SOT 963 6 pins package 1x0.8mm pitch 0.35mm SOT-1123 small outline package; 16 leads; body width 3 mm; (see NXP SSOP-TSSOP-VSO-REFLOW.pdf and sot370-1_po.pdf SSOP56: plastic shrink small outline package; 24 leads; body width 3.9 mm; lead pitch 0.635; (see NXP SSOP-TSSOP-VSO-REFLOW.pdf and sot552-1_po.pdf 14-Lead Plastic Dual Flat, No Lead Package - 4x4x0.9 mm Body [QFN] with corner pads and trace routing to de-bodge the pots. 's notes on updating the fireball for rev 2.
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